1. Field of the Invention
The present invention relates to methods for forming high density integrated circuit devices and to high density integrated circuit devices such as non-volatile memories formed by such methods.
2. Description of the Related Art
Certain integrated circuit memory devices consist of an array of memory cells positioned at the intersections between an array of parallel buried conducting lines formed in a semiconductor substrate and a perpendicular array of conductive wiring lines formed above the substrate. A prominent example of such memory devices is the type of read only memory (ROM) known as the mask ROM, although other memory devices including EEPROMs might have generally similar configurations. A small portion (four cells) of a mask ROM is illustrated in plan view FIG. 1 and a still smaller portion is illustrated in partial cross section in FIG. 2. The FIG. 1 mask ROM is formed on the P-type surface of a silicon substrate 10 and includes an array of buried bit lines 12, 14, 16 formed as N-type regions by selective doping of the substrate 10. An array of parallel polysilicon word lines 18, 20 extends over the surface of the substrate 10 in a direction generally perpendicular to the array of bit lines 12, 14, 16. The array of word lines is separated from the substrate by a layer of silicon oxide.
Most often, the ROM of FIG. 1 utilizes a shared bit line architecture. Thus, bit lines 12, 14, 16 act as source/drain regions for the memory field effect transistors (FETs), word lines 18, 20 act as the gates of the memory transistors, and regions 22, 24, 26, 28 in the substrate under the word lines and between adjacent bit lines act as the channel regions of the memory transistors. Information is stored in the individual memory transistors by altering the transport characteristics of the individual transistors in a manner that can be sensed using the appropriate pair of adjacent bit lines as source/drain contacts for the individual FET. One characteristic of the memory transistor that might be altered to store information is the transistor's threshold voltage. Consequently, the illustrated ROM may be programmed by selecting the threshold voltage of the various memory transistors of the array. The threshold voltages of each of the transistors of the array may be selected by ion implanting impurities through a code mask which ensures that the code implantation reaches only the channels of the FETs that are to have their threshold voltage altered. When programming of the mask ROM is accomplished using the selective implantation of dopants into the channels of the FETs, data stored at the memory locations can be read out by applying an appropriate signal to the particular word line that functions as the gate electrode for the transistor to select a row of memory transistors and then sensing the threshold voltage of the selected FET using the appropriate pair of adjacent bit lines as source/drain contacts for the FET.
FIG. 2 illustrates aspects of the structure of the ROM that are particularly related to the formation of the ROM. Typically, the array of buried bit lines is formed at an early stage in processing by forming an appropriate mask over the substrate and implanting N-type impurities into the substrate to define portions of the substrate that will become the conducting bit lines 12, 14, 16. The implanted substrate is then placed in a high temperature oxidizing environment to activate the bit line implantation and to grow an oxide layer over the surface of the substrate. The oxide layer consists of comparatively thin gate oxide layers 30 over the channel regions 22, 24 and thicker oxide layers 32 over the bit lines 12, 14, 16. Thicker oxide grows over the bit lines 12, 14, 16 because the heavily doped N-type silicon of the bit lines oxidizes at a much faster rate than does the more lightly doped P-type channel regions 22, 24. After the oxide layer is grown, a layer of doped polysilicon is provided over the oxide layer and patterned to define the gate electrodes of the memory transistors, such as the illustrated gate electrode 18. The gate electrodes also function as word lines for the ROM.
As the ROM illustrated in FIGS. 1 and 2 is made smaller, the width of the buried bit lines 12, 14, 16 becomes smaller and the spacing between the bit lines becomes smaller. Smaller bit lines are more resistive and so tend to reduce the speed at which data can be accessed from the ROM. More closely spaced bit lines have an increased likelihood of experiencing punchthrough at normal operating voltages. Punchthrough in FETs occurs when, for a given applied voltage, there are too few carriers in the channel region to maintain a distinct channel in the FET and the depletion region associated with the source and drain regions extends completely across the channel. For a FET after the onset of punchthrough, application of signals to the gate electrode effects little or no control on the FET. Punchthrough limits the maximum voltage that can be applied to short channel FETs and also limits how small a channel region can be made for certain combinations of source/drain and channel doping levels. As a practical matter, punchthrough limits how small memory transistors can be made in a high volume manufacturing environment. It is therefore desirable to produce a buried bit line structure more compatible with smaller device geometries so that reduced design rules do not result in unacceptable memory performance.